Invention Grant
- Patent Title: Circuit structure with vertical double gate
- Patent Title (中): 电路结构采用垂直双门
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Application No.: US13213786Application Date: 2011-08-19
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Publication No.: US08476704B2Publication Date: 2013-07-02
- Inventor: Jeng Hsing Jang , Yi Nan Chen , Hsien Wen Liu
- Applicant: Jeng Hsing Jang , Yi Nan Chen , Hsien Wen Liu
- Applicant Address: TW Tao-Yuan Hsien
- Assignee: Nan Ya Technology Corporation
- Current Assignee: Nan Ya Technology Corporation
- Current Assignee Address: TW Tao-Yuan Hsien
- Agency: Stites & Harbison PLLC
- Agent Juan Carlos A. Marquez, Esq.
- Main IPC: H01L29/78
- IPC: H01L29/78
Abstract:
A circuit structure including a semiconductor substrate having a depression; a first insulating layer positioned on the surface of the depression; a bottom conductor positioned in a bottom portion of the depression, wherein the bottom conductor is connected to an external bias through a plurality of longer vertical contact plugs; an upper conductor positioned in an upper portion of the depression, wherein the upper conductor is connected to a plurality of shorter vertical contact plugs, and a top surface of the upper conductor is higher than a depression-bearing surface of the semiconductor substrate; and a second insulating layer positioned between the bottom conductor and the upper conductor.
Public/Granted literature
- US20130043529A1 Circuit Structure with Vertical Double Gate Public/Granted day:2013-02-21
Information query
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