Invention Grant
- Patent Title: CMOS having a SiC/SiGe alloy stack
- Patent Title (中): 具有SiC / SiGe合金叠层的CMOS
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Application No.: US13343472Application Date: 2012-01-04
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Publication No.: US08476706B1Publication Date: 2013-07-02
- Inventor: Dureseti Chidambarrao , Brian J. Greene , Yue Liang , Xiaojun Yu
- Applicant: Dureseti Chidambarrao , Brian J. Greene , Yue Liang , Xiaojun Yu
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Scully, Scott, Murphy & Presser, P.C.
- Agent Joseph P. Abate, Esq.
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119 ; H01L27/01 ; H01L27/12 ; H01L31/0392

Abstract:
A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer.
Public/Granted literature
- US20130168695A1 CMOS HAVING A SIC/SIGE ALLOY STACK Public/Granted day:2013-07-04
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