Invention Grant
- Patent Title: Electroplated posts with reduced topography and stress
- Patent Title (中): 具有减少地形和压力的电镀柱
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Application No.: US13288161Application Date: 2011-11-03
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Publication No.: US08476760B2Publication Date: 2013-07-02
- Inventor: Manoj K. Jain , Sreenivasan Koduri
- Applicant: Manoj K. Jain , Sreenivasan Koduri
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/00 ; H01L21/44
Abstract:
Bond pads on an integrated circuit are provided with planarizing dielectric structures to permit the electroplating of metal posts having planar top surfaces. The metal posts contact at least three sides of the planarizing dielectric structures. The planarizing dielectric structures can be used on integrated circuits having bond pads of different sizes to electroplate metal posts having the same height.
Public/Granted literature
- US20120112343A1 ELECTROPLATED POSTS WITH REDUCED TOPOGRAPHY AND STRESS Public/Granted day:2012-05-10
Information query
IPC分类:
