An integrated circuit for use in a power supply includes a drive signal generator, a first delay, a second delay, a comparator, a first logic, a first short on time detector, and a second logic. The drive signal generator generates a drive signal to control a switch in response to a clock signal. The short on time detector sets the first latch indicating that an on time of the switch is a short on time. The second logic is coupled to detect long pulses of the drive signal to reset the first latch indicating that the on time of the switch is not a short on time. An on time of the drive signal is a short on time if a switch current of the switch exceeds a current limit after a sum of a leading edge blanking period and a current limit delay time period.