A memory array compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory array includes a first sense amplifier (700) having a first bit line (754) extending in a first direction and a second bit line (752) extending in a second direction parallel to the first bit line. A second sense amplifier (704) has a third bit line (756) adjacent and parallel to the first bit line. The third bit line remains inactive while the first bit line is active.