• Patent Title: Cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation
  • Application No.: US13716986
    Application Date: 2012-12-17
  • Publication No.: US08479084B2
    Publication Date: 2013-07-02
  • Inventor: Phil Northcott
  • Applicant: PMC-Sierra US, Inc.
  • Applicant Address: US CA Santa Clara
  • Assignee: PMC-Sierra US, Inc.
  • Current Assignee: PMC-Sierra US, Inc.
  • Current Assignee Address: US CA Santa Clara
  • Agent Dennis R. Haszko
  • Main IPC: H03M13/00
  • IPC: H03M13/00
Cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation
Abstract:
A method and system are provided for forward error correction. Embodiments of the present disclosure provide a strong FEC algorithm that performs similarly to RS(255,239) when a simple decoder is used, and scales up linearly to a full-scale decoder that outperforms all 7% algorithms currently in G.975.1. The Forward Error Correction code is suitable for use in optical transport networks (OTN) and other applications requiring high decode performance and high code rate. Embodiments of the present disclosure provide an FEC code that is a cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation.
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