Invention Grant
- Patent Title: Methods for integrated circuit fabrication with protective coating for planarization
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Application No.: US13207627Application Date: 2011-08-11
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Publication No.: US08479384B2Publication Date: 2013-07-09
- Inventor: Mirzafer Abatchev , David Wells , Baosuo Zhou , Krupakar M. Subramanian
- Applicant: Mirzafer Abatchev , David Wells , Baosuo Zhou , Krupakar M. Subramanian
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Knobbe, Martens, Olson & Bear LLP
- Main IPC: H05K3/20
- IPC: H05K3/20

Abstract:
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
Public/Granted literature
- US20110294294A1 PROTECTIVE COATING FOR PLANARIZATION Public/Granted day:2011-12-01
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