Invention Grant
- Patent Title: Method for manufacturing semiconductor device
- Patent Title (中): 制造半导体器件的方法
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Application No.: US12958994Application Date: 2010-12-02
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Publication No.: US08480934B2Publication Date: 2013-07-09
- Inventor: Koji Hashimoto
- Applicant: Koji Hashimoto
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, LLP
- Priority: JP2009-274854 20091202
- Main IPC: B29C45/76
- IPC: B29C45/76 ; B28B3/00 ; H05K1/00 ; G06F19/00 ; G06F17/50

Abstract:
According to one embodiment, a manufacturing method includes performing lithography processes for manufacturing a semiconductor device that includes a three-dimensional stacked device. The stacked device includes layers stacked above a substrate. Each of the layers includes a device circuit. The lithography processes include a lithography process for forming a lower layer of the layers by using a first original plate that has quality not less than a certain level. The first original plate is selected from original plates. Each of the original plates includes a pattern corresponding to the device circuit. The original plates are ranked according to quality based on defect. The lithography processes further include a lithography process for forming a higher layer of the layers by using a second original plate that has quality lower than the certain level. The second original plate is selected from the original plates.
Public/Granted literature
- US20110129780A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2011-06-02
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