Invention Grant
- Patent Title: JFET device structures and methods for fabricating the same
- Patent Title (中): JFET器件结构及其制造方法
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Application No.: US12333012Application Date: 2008-12-11
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Publication No.: US08481372B2Publication Date: 2013-07-09
- Inventor: Chandra Mouli
- Applicant: Chandra Mouli
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder
- Main IPC: H01L21/337
- IPC: H01L21/337

Abstract:
In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.
Public/Granted literature
- US20100148226A1 JFET DEVICE STRUCTURES AND METHODS FOR FABRICATING THE SAME Public/Granted day:2010-06-17
Information query
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