Method of forming semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate

Invention Grant

US08481383B2 Method of forming semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate 有权

Title translation: 在侧壁绝缘膜和半导体衬底之间形成具有缓冲层的半导体器件的方法

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Patent Title: Method of forming semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate
Patent Title (中): 在侧壁绝缘膜和半导体衬底之间形成具有缓冲层的半导体器件的方法
Application No.: US13024988

Application Date: 2011-02-10
Publication No.: US08481383B2

Publication Date: 2013-07-09
Inventor: Hiroyuki Ohta , Katsuaki Ookoshi
Applicant: Hiroyuki Ohta , Katsuaki Ookoshi
Applicant Address: JP Yokohama
Assignee: Fujitsu Semiconductor Limited
Current Assignee: Fujitsu Semiconductor Limited
Current Assignee Address: JP Yokohama
Agency: Fujitsu Patent Center
Priority: JP2006-336269 20061213
Main IPC: H01L21/8238
IPC: H01L21/8238 ; H01L27/092

Method of forming semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate

Abstract:

A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

Abstract(Chinese):

半导体器件包括NMOS晶体管和PMOS晶体管。 NMOS晶体管包括形成在硅衬底中的沟道区，形成在与沟道区相对应的栅极绝缘膜上的栅电极，以及形成在硅衬底中的沟道区的源极区和漏区，位于其间。 PMOS晶体管包括形成在硅衬底中的另一沟道区，与另一沟道区相对应的另一栅极电极上形成的另一栅电极，以及形成在硅衬底中的另一源极区和另一漏极区，其另一沟道区位于其间。栅电极具有第一侧壁绝缘膜。另一个栅电极具有第二侧壁绝缘膜。第二侧壁绝缘膜和硅衬底之间的距离大于第一侧壁绝缘膜和硅衬底之间的距离。

Public/Granted literature

US20110136307A1 SEMICONDUCTOR DEVICE HAVING BUFFER LAYER BETWEEN SIDEWALL INSULATING FILM AND SEMICONDUCTOR SUBSTRATE Public/Granted day:2011-06-09

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS