Invention Grant
US08481390B2 Method for forming impurity region of vertical transistor and method for fabricating vertical transistor using the same
有权
用于形成垂直晶体管的杂质区域的方法及使用其制造垂直晶体管的方法
- Patent Title: Method for forming impurity region of vertical transistor and method for fabricating vertical transistor using the same
- Patent Title (中): 用于形成垂直晶体管的杂质区域的方法及使用其制造垂直晶体管的方法
-
Application No.: US13084220Application Date: 2011-04-11
-
Publication No.: US08481390B2Publication Date: 2013-07-09
- Inventor: Yong Seok Eun , Tae Kyun Kim , Kyong Bong Rouh , Eun Shil Park
- Applicant: Yong Seok Eun , Tae Kyun Kim , Kyong Bong Rouh , Eun Shil Park
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: William Park & Associates Patent Ltd.
- Priority: KR10-2010-0055296 20100611
- Main IPC: H01L21/336
- IPC: H01L21/336
Abstract:
A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.
Public/Granted literature
Information query
IPC分类:
