Invention Grant
- Patent Title: Processes for fabricating heterostructures
- Patent Title (中): 制造异质结构的工艺
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Application No.: US13341462Application Date: 2011-12-30
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Publication No.: US08481407B2Publication Date: 2013-07-09
- Inventor: Bruce Faure
- Applicant: Bruce Faure
- Applicant Address: FR Bernin
- Assignee: Soitec
- Current Assignee: Soitec
- Current Assignee Address: FR Bernin
- Agency: TraskBritt
- Priority: FR0853150 20080515
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/26
Abstract:
The invention relates to a process for fabricating a heterostructure. This process comprises heating an intermediate heterostructure. The intermediate heterostructure comprises a crystalline strain relaxation layer interposed directly between a first substrate and a strained layer of crystalline semiconductor material. The process further comprises causing plastic deformation of the crystalline strain relaxation layer and elastic deformation of the strained layer of crystalline semiconductor material to at least partially relax the strained layer of crystalline semiconductor material.
Public/Granted literature
- US20120100691A1 PROCESSES FOR FABRICATING HETEROSTRUCTURES Public/Granted day:2012-04-26
Information query
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