Invention Grant
US08481420B2 Integrated circuit packaging system with lead frame stacking module and method of manufacture thereof
有权
具有引线框架堆叠模块的集成电路封装系统及其制造方法
- Patent Title: Integrated circuit packaging system with lead frame stacking module and method of manufacture thereof
- Patent Title (中): 具有引线框架堆叠模块的集成电路封装系统及其制造方法
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Application No.: US13048859Application Date: 2011-03-15
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Publication No.: US08481420B2Publication Date: 2013-07-09
- Inventor: Jong-Woo Ha , DaeSik Choi , Byoung Wook Jang
- Applicant: Jong-Woo Ha , DaeSik Choi , Byoung Wook Jang
- Applicant Address: SG Singapore
- Assignee: STATS Chippac Ltd.
- Current Assignee: STATS Chippac Ltd.
- Current Assignee Address: SG Singapore
- Agency: Ishimaru & Associates LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/48

Abstract:
A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit die having an active side and a passive side; providing a contact pad having a top side oriented in a same direction as the passive side; connecting an inner bond wire to the contact pad and the integrated circuit die; and molding a stacking structure around the contact pad, the inner bond wire, and the integrated circuit die with the passive side and the top side exposed, and the stacking structure having a top structure surface on top and adjacent to or below the integrated circuit die, and a horizontal member under the integrated circuit die and forming a cavity.
Public/Granted literature
- US20120235307A1 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEAD FRAME STACKING MODULE AND METHOD OF MANUFACTURE THEREOF Public/Granted day:2012-09-20
Information query
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