Invention Grant
- Patent Title: Resistance change memory and manufacturing method thereof
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Application No.: US12886118Application Date: 2010-09-20
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Publication No.: US08481988B2Publication Date: 2013-07-09
- Inventor: Takeshi Sonehara
- Applicant: Takeshi Sonehara
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2009-276636 20091204
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
According to one embodiment, a resistance change memory includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit which is provided between the first interconnect line and the second interconnect line and which includes a non-ohmic element and a memory element, the non-ohmic element including a conductive layer provided on at least one of first and second ends of the cell unit and a silicon portion provided between the first and second ends, the memory element being connected to the non-ohmic element via the conductive layer and storing data in accordance with a reversible change in a resistance state, wherein the non-ohmic element includes a first silicon germanium region in the silicon portion.
Public/Granted literature
- US20110133149A1 RESISTANCE CHANGE MEMORY AND MANUFACTURING METHOD THEREOF Public/Granted day:2011-06-09
Information query
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