Invention Grant
- Patent Title: Semiconductor structure and method of fabricating the semiconductor structure
- Patent Title (中): 半导体结构及其制造方法
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Application No.: US13412959Application Date: 2012-03-06
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Publication No.: US08482041B2Publication Date: 2013-07-09
- Inventor: Fujio Masuoka , Keon Jae Lee
- Applicant: Fujio Masuoka , Keon Jae Lee
- Applicant Address: SG Peninsula Plaza
- Assignee: Unisantis Electronics Singapore Pte Ltd.
- Current Assignee: Unisantis Electronics Singapore Pte Ltd.
- Current Assignee Address: SG Peninsula Plaza
- Agency: Brinks Hofer Gilson & Lione
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
In contrast to a conventional planar CMOS technique in design and fabrication for a field-effect transistor (FET), the present invention provides an SGT CMOS device formed on a conventional substrate using various crystal planes in association with a channel type and a pillar shape of an FET, without a need for a complicated device fabrication process. Further, differently from a design technique of changing a surface orientation in each planar FET, the present invention is designed to change a surface orientation in each SGT to achieve improvement in carrier mobility. Thus, a plurality of SGTs having various crystal planes can be formed on a common substrate to achieve a plurality of different carrier mobilities so as to obtain desired performance.
Public/Granted literature
- US20120171825A1 SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SEMICONDUCTOR STRUCTURE Public/Granted day:2012-07-05
Information query
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