Invention Grant
- Patent Title: MOS transistor with a reduced on-resistance and area product
- Patent Title (中): MOS晶体管具有降低的导通电阻和面积产品
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Application No.: US12313924Application Date: 2008-11-25
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Publication No.: US08482065B2Publication Date: 2013-07-09
- Inventor: Zachary K. Lee
- Applicant: Zachary K. Lee
- Applicant Address: US CA Newport Beach
- Assignee: Newport Fab, LLC
- Current Assignee: Newport Fab, LLC
- Current Assignee Address: US CA Newport Beach
- Agency: Farjami & Farjami LLP
- Main IPC: H01L29/66
- IPC: H01L29/66

Abstract:
According to an exemplary embodiment, a MOS transistor, such as an LDMOS transistor, includes a gate having a first side situated immediately adjacent to at least one source region and at least one body tie region. The MOS transistor further includes a drain region spaced apart from a second side of the gate. The MOS transistor further includes a body region in contact with the at least one body tie region, where the at least one body tie region is electrically connected to the at least one source region. The MOS transistor further includes a lightly doped region separating the drain region from the second side of the gate. The lightly doped region can isolate the body region from an underlying substrate.
Public/Granted literature
- US20100127326A1 MOS transistor with a reduced on-resistance and area product Public/Granted day:2010-05-27
Information query
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