Invention Grant
- Patent Title: Semiconductor device manufacturing method and semiconductor device
- Patent Title (中): 半导体器件制造方法和半导体器件
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Application No.: US13137599Application Date: 2011-08-29
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Publication No.: US08482074B2Publication Date: 2013-07-09
- Inventor: Masayuki Tajiri , Takayoshi Hashimoto , Hisashi Yonemoto , Toyohiro Harazono
- Applicant: Masayuki Tajiri , Takayoshi Hashimoto , Hisashi Yonemoto , Toyohiro Harazono
- Applicant Address: JP Osaka
- Assignee: Sharp Kabushiki Kaisha
- Current Assignee: Sharp Kabushiki Kaisha
- Current Assignee Address: JP Osaka
- Agency: Harness, Dickey & Pierce, PLC
- Priority: JP2009-190456 20090819
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, a liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.
Public/Granted literature
- US20120139052A1 Semiconductor device manufacturing method and semiconductor device Public/Granted day:2012-06-07
Information query
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