Invention Grant
US08482123B2 Stress reduction in chip packaging by using a low-temperature chip-package connection regime 有权
通过使用低温芯片封装连接方式降低芯片封装的压力

Stress reduction in chip packaging by using a low-temperature chip-package connection regime
Abstract:
A semiconductor chip and a package substrate may be directly connected on the basis of form closure by providing appropriately shaped complementary contact structures in the semiconductor chip and the package substrate. Consequently, solder material may no longer be required and thus any elevated temperatures during the assembly process may be avoided, which may conventionally result in significant stress forces, thereby creating damage, in particular in very complex metallization systems.
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