Invention Grant
US08482123B2 Stress reduction in chip packaging by using a low-temperature chip-package connection regime
有权
通过使用低温芯片封装连接方式降低芯片封装的压力
- Patent Title: Stress reduction in chip packaging by using a low-temperature chip-package connection regime
- Patent Title (中): 通过使用低温芯片封装连接方式降低芯片封装的压力
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Application No.: US13179643Application Date: 2011-07-11
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Publication No.: US08482123B2Publication Date: 2013-07-09
- Inventor: Michael Grillberger , Matthias Lehr , Thomas Werner
- Applicant: Michael Grillberger , Matthias Lehr , Thomas Werner
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE102010040065 20100831
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A semiconductor chip and a package substrate may be directly connected on the basis of form closure by providing appropriately shaped complementary contact structures in the semiconductor chip and the package substrate. Consequently, solder material may no longer be required and thus any elevated temperatures during the assembly process may be avoided, which may conventionally result in significant stress forces, thereby creating damage, in particular in very complex metallization systems.
Public/Granted literature
- US20120049350A1 Stress Reduction in Chip Packaging by Using a Low-Temperature Chip-Package Connection Regime Public/Granted day:2012-03-01
Information query
IPC分类: