Invention Grant
- Patent Title: Fan-out chip scale package
- Patent Title (中): 扇出芯片级封装
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Application No.: US12648634Application Date: 2009-12-29
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Publication No.: US08482136B2Publication Date: 2013-07-09
- Inventor: Jan Gulpen , Tonny Kamphuis , Pieter Hochstenbach , Leo van Gemert , Eric van Grunsven , Marc de Samber
- Applicant: Jan Gulpen , Tonny Kamphuis , Pieter Hochstenbach , Leo van Gemert , Eric van Grunsven , Marc de Samber
- Applicant Address: NL Eindhoven
- Assignee: NXP B.V.
- Current Assignee: NXP B.V.
- Current Assignee Address: NL Eindhoven
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40
Abstract:
A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.
Public/Granted literature
- US20110156237A1 FAN-OUT CHIP SCALE PACKAGE Public/Granted day:2011-06-30
Information query
IPC分类:
