Invention Grant
- Patent Title: I/O circuit calibration method and associated apparatus
- Patent Title (中): I / O电路校准方法及相关设备
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Application No.: US12889017Application Date: 2010-09-23
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Publication No.: US08482293B2Publication Date: 2013-07-09
- Inventor: Eer-Wen Tyan , Ming-Chieh Yeh
- Applicant: Eer-Wen Tyan , Ming-Chieh Yeh
- Applicant Address: TW Hsinchu Hsien
- Assignee: MStar Semiconductor, Inc.
- Current Assignee: MStar Semiconductor, Inc.
- Current Assignee Address: TW Hsinchu Hsien
- Agency: Edell, Shapiro & Finnan, LLC
- Priority: TW98133229A 20090930
- Main IPC: G01R35/00
- IPC: G01R35/00

Abstract:
An I/O calibration method and an apparatus are provided for calibrating a driving impedance at an output end of an I/O circuit in a chip. The chip further includes a plurality of basic impedances and a non-volatile memory. The I/O circuit calibration method includes: measuring an impedance value of one basic impedance and recording the measured impedance value in the non-volatile memory; synthesizing a calibration impedance by selectively conducting the basic impedance(s); adjusting the number of the conducted basic impedance(s) in the calibration impedance and estimating an impedance value of the driving impedance according to the measured result and a voltage divided by the calibration impedance and the driving impedance at the output end.
Public/Granted literature
- US20110074520A1 I/O Circuit Calibration Method and Associated Apparatus Public/Granted day:2011-03-31
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