A logic circuit has a first logic element (“LE”) including a first lookup table (“LUT”), where the first LUT is operable to produce a carry from a first set of bits of at least two numbers. The logic circuit also has a second LE including a second LUT, where the second LUT is operable to produce a sum from a second set of bits of the at least two numbers. The second LE also includes an adder coupled directly to the first LUT and coupled to the second LUT, where the adder is operable to add the carry and the sum. The at least two numbers may be three numbers, but the logic circuit includes a set of connections operable to programmably interconnect selected inputs so that the logic circuit is operable to add only two numbers. The logic circuit may be incorporated in a programmable logic device.