A memory array compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory array includes a first sense amplifier (700) having a signal bit line (710) extending in a first direction and having a memory cell (714) suitable for a read operation. A second sense amplifier (704) has a second bit line (706) adjacent and parallel to the signal bit line. The second bit line receives a precharge voltage during the read operation. A third sense amplifier (704) has a third bit line (706) adjacent and parallel to the signal bit line. The third bit line receives the precharge voltage during the read operation.