Invention Grant
- Patent Title: Memory kink checking
- Patent Title (中): 内存扭结检查
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Application No.: US12559275Application Date: 2009-09-14
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Publication No.: US08482975B2Publication Date: 2013-07-09
- Inventor: Uday Chandrasekhar , Mark Helm
- Applicant: Uday Chandrasekhar , Mark Helm
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a programming status of a first memory cell, wherein the first memory cell is coupled to the first data line and to a selected access line. An effect on a second data line is determined, due at least in part to the voltage applied to the first data line and a capacitive coupling between at least the first data line and the second data line, wherein the second data line is coupled to a second memory cell, the second memory cell is adjacent to the first memory cell, and the second memory cell is coupled to the selected access line. A kink correction is applied to the second data line, responsive to the determined effect, during a subsequent programming pulse applied to the second memory cell.
Public/Granted literature
- US20110063919A1 MEMORY KINK CHECKING Public/Granted day:2011-03-17
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