Invention Grant
- Patent Title: High-speed receiver architecture
- Patent Title (中): 高速接收机架构
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Application No.: US12056084Application Date: 2008-03-26
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Publication No.: US08483343B2Publication Date: 2013-07-09
- Inventor: Oscar E. Agazzi , Diego E. Crivelli , Hugo S. Carrer , Mario R. Hueda , German C. Luna , Carl Grace
- Applicant: Oscar E. Agazzi , Diego E. Crivelli , Hugo S. Carrer , Mario R. Hueda , German C. Luna , Carl Grace
- Applicant Address: US CA Irvine
- Assignee: ClariPhy Communications, Inc.
- Current Assignee: ClariPhy Communications, Inc.
- Current Assignee Address: US CA Irvine
- Agency: Fenwick & West LLP
- Main IPC: H04L7/00
- IPC: H04L7/00
Abstract:
A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
Public/Granted literature
- US20080240325A1 High-Speed Receiver Architecture Public/Granted day:2008-10-02
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