An apparatus comprises a memory and a processor coupled to the memory. The memory stores first and second orders. The first order is associated with a product and comprises a displayed quantity and a reserved quantity. The second order is associated with the product and comprises a displayed quantity and a reserved quantity. The processor receives a counterorder associated with the product. The processor fills the displayed quantity of the first order with a corresponding portion of the counterorder, and fills the displayed quantity of the second order with a corresponding portion of the counterorder. The processor allocates a first additional portion of the counterorder to the first order. The first additional portion is based at least in part on a ratio of the displayed quantity of the first order to a sum of the displayed quantity of the first order and the displayed quantity of the second order.