Invention Grant
- Patent Title: Digital architecture for DFT/IDFT hardware
- Patent Title (中): DFT / IDFT硬件的数字架构
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Application No.: US11801903Application Date: 2007-05-11
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Publication No.: US08484278B2Publication Date: 2013-07-09
- Inventor: Baijayanta Ray , Venkataraghavan Punnapakkam Krishnan , Sriram Balasubramanian , Dalavaipatnam Rangarao Seetharaman
- Applicant: Baijayanta Ray , Venkataraghavan Punnapakkam Krishnan , Sriram Balasubramanian , Dalavaipatnam Rangarao Seetharaman
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Park, Vaughan, Fleming & Dowler, LLP
- Agent Laxman Saharsrabuddhe
- Main IPC: G06F15/00
- IPC: G06F15/00

Abstract:
Embodiments of the present invention can provide circuits and systems for computing a discrete Fourier transform (DFT) or an inverse discrete Fourier transform (IDFT). An embodiment includes an input circuit, an intermediate circuit, an output circuit, and an accumulator circuit. The input circuit can receive a set of input values, and can use a first set of degenerate rotators to generate a first set of intermediate values. The intermediate circuit can receive the first set of intermediate values, and can use a set of CORDICs (coordinate rotation digital computers) to generate a second set of intermediate values. The output circuit can receive the second set of intermediate values, and can use a second set of degenerate rotators to generate a third set of intermediate values. The accumulator circuit can receive the third set of intermediate values, and can use a set of accumulators to generate a set of output values.
Public/Granted literature
- US20080281894A1 Digital architecture for DFT/IDFT hardware Public/Granted day:2008-11-13
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