Invention Grant
- Patent Title: Inter-thread trace alignment method and system for a multi-threaded processor
- Patent Title (中): 多线程处理器的线程跟踪对齐方法和系统
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Application No.: US11734199Application Date: 2007-04-11
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Publication No.: US08484516B2Publication Date: 2013-07-09
- Inventor: Louis Achille Giannini , William Anderson , Xufeng Chen
- Applicant: Louis Achille Giannini , William Anderson , Xufeng Chen
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Peter Michael Kamarchik; Nicholas J. Pauley; Joseph Agusta
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Inter-thread trace alignment with execution trace processing includes recording timing data relating to a common predetermined event. Such an event may be the number of cycles since a last thread initiated execution tracing or the number of cycles since all threads terminated execution tracing. The number of cycles at which a thread initiates execution tracing is referenced to the common predetermined event for maintaining the timing of execution tracing. The data relating to the common predetermined event is then updated to associate with the time at which the thread initiated execution tracing. The result is to permit aligning the timing data associated with all threads. Interrelated records permit reconstructing interdependent execution tracing information for threads operating in the multi-threaded processor, as well as synchronizing timing data for all operating threads.
Public/Granted literature
- US20080256396A1 INTER-THREAD TRACE ALIGNMENT METHOD AND SYSTEM FOR A MULTI-THREADED PROCESSOR Public/Granted day:2008-10-16
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