Invention Grant
- Patent Title: Sequential digital circuitry with test scan
- Patent Title (中): 具有测试扫描的顺序数字电路
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Application No.: US12729826Application Date: 2010-03-23
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Publication No.: US08484523B2Publication Date: 2013-07-09
- Inventor: Ravindraraj Ramaraju , Prashant U. Kenkare , Gary A. Mussemann , Mihir S. Sabnis
- Applicant: Ravindraraj Ramaraju , Prashant U. Kenkare , Gary A. Mussemann , Mihir S. Sabnis
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent James L. Clingan, Jr.
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.
Public/Granted literature
- US20110239069A1 SEQUENTIAL DIGITAL CIRCUITRY WITH TEST SCAN Public/Granted day:2011-09-29
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