Invention Grant
US08484524B2 Integrated circuit with self-test feature for validating functionality of external interfaces 失效
具有自检功能的集成电路,用于验证外部接口的功能

  • Patent Title: Integrated circuit with self-test feature for validating functionality of external interfaces
  • Patent Title (中): 具有自检功能的集成电路,用于验证外部接口的功能
  • Application No.: US11842396
    Application Date: 2007-08-21
  • Publication No.: US08484524B2
    Publication Date: 2013-07-09
  • Inventor: Srinivas Maddali
  • Applicant: Srinivas Maddali
  • Applicant Address: US CA San Diego
  • Assignee: QUALCOMM Incorporated
  • Current Assignee: QUALCOMM Incorporated
  • Current Assignee Address: US CA San Diego
  • Agent Peter Michael Kamarchik; Nicholas J. Pauley; Joseph Agusta
  • Main IPC: G01R31/28
  • IPC: G01R31/28 G06F11/00
Integrated circuit with self-test feature for validating functionality of external interfaces
Abstract:
This disclosure describes an integrated circuit with self-test features for validating functionality of external interfaces. Example external interfaces include memory interfaces and bus interfaces, such as a peripheral component interconnect (PCI) bus, an advanced high-performance bus (AHB), an advanced extensible interface (AXI) bus, and other external interfaces that operate a high frequency, e.g., 200 MHz or greater. Test logic may be embedded on the integrated circuit and configured to validate functionality of external interfaces while receiving power and non-test signals from external test equipment. Thus, external test equipment may not supply high frequency test signals to the integrated circuit. The external test equipment may, however, independently validate functionality of a pin interface of the integrated circuit. As a result, the integrated circuit may reduce cost and time required to verify functionality and timing of the external interfaces.
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