Software method to identify which transistor gates float, and why, in complex, multi-transistor, electronic circuit designs. Transistor gates suspected of floating are analyzed by expanding backwards to build a logical tree representation of the previous predecessor circuit portions which drive that suspect gate. The method checks if the previous level of predecessor circuit node states earlier in the circuit show up more than once with different values, thus indicating by logical conflict that a particular floating suspect gate does not float. It then repeats this back-trace analysis for the next previous level of predecessor circuit portions, further seeking logical conflicts within the expanding logic tree. This is continued until either no predecessor circuit portion that can cause the suspect gate to float is found, or until a portion that does cause the suspect gate to float is found, in which case the suspect gate is identified as a probable floating gate.