Invention Grant
- Patent Title: Integrated circuit manufacturing method, design method and program
- Patent Title (中): 集成电路制造方法,设计方法和程序
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Application No.: US13075789Application Date: 2011-03-30
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Publication No.: US08484597B2Publication Date: 2013-07-09
- Inventor: Hiroshi Arimoto
- Applicant: Hiroshi Arimoto
- Applicant Address: JP Yokohama
- Assignee: Fujitsu Semiconductor Limited
- Current Assignee: Fujitsu Semiconductor Limited
- Current Assignee Address: JP Yokohama
- Agency: Arent Fox LLP
- Priority: JP2010-091722 20100412
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
An integrated circuit manufacturing method comprising: calculating a threshold value from a value of a parameter which characterizes at least a part of a design pattern shape of a transistor on the target path; calculating a difference between the calculated threshold value and a target threshold value; calculating a change quantity of a gate length corresponding to the difference between the threshold value and the target threshold value according to the functional relation between the threshold value of the transistor and the gate length, which is determined based on the empirical value or the experimental value; reducing, by the change quantity, the gate length of the transistor on the target path; and manufacturing an integrated circuit on the basis of design information of the circuit including the transistor of which the gate length is changed.
Public/Granted literature
- US20110252391A1 INTEGRATED CIRCUIT MANUFACTURING METHOD, DESIGN METHOD AND PROGRAM Public/Granted day:2011-10-13
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