Invention Grant
- Patent Title: Simultaneous wafer bonding and interconnect joining
- Patent Title (中): 同时晶片接合和互连接合
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Application No.: US13076969Application Date: 2011-03-31
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Publication No.: US08486758B2Publication Date: 2013-07-16
- Inventor: Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
- Applicant: Vage Oganesian , Belgacem Haba , Ilyas Mohammed , Piyush Savalia , Craig Mitchell
- Applicant Address: US CA San Jose
- Assignee: Tessera, Inc.
- Current Assignee: Tessera, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/48

Abstract:
Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.
Public/Granted literature
- US20120153488A1 SIMULTANEOUS WAFER BONDING AND INTERCONNECT JOINING Public/Granted day:2012-06-21
Information query
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