Invention Grant
US08486759B2 Method for forming terminal of stacked package element and method for forming stacked package
有权
层叠封装元件的端子的形成方法以及堆叠封装的形成方法
- Patent Title: Method for forming terminal of stacked package element and method for forming stacked package
- Patent Title (中): 层叠封装元件的端子的形成方法以及堆叠封装的形成方法
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Application No.: US13241724Application Date: 2011-09-23
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Publication No.: US08486759B2Publication Date: 2013-07-16
- Inventor: Masato Ikeda
- Applicant: Masato Ikeda
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Nihon Micronics
- Current Assignee: Kabushiki Kaisha Nihon Micronics
- Current Assignee Address: JP Tokyo
- Agency: Bacon & Thomas, PLLC
- Main IPC: H01L21/50
- IPC: H01L21/50
Abstract:
A semiconductor chip module having high degree of freedom in assignment of a circuit to each semiconductor chip and in position of a connection terminal of each semiconductor chip is provided. The present invention relates to a semiconductor chip module in which a plurality of semiconductor chips, each provided on the side face thereof with a part of a connection terminal coupled with a circuit pattern formed on the front face, have been stacked and bonded. Connection terminal portions on the side faces of the respective semiconductor chips are interconnected by a wiring pattern. The connection terminal on the semiconductor chip is led from the front face to the side face and formed by applying spraying of a conductive material in a mist state.
Public/Granted literature
- US20120021562A1 METHOD FOR FORMING TERMINAL OF STACKED PACKAGE ELEMENT AND METHOD FOR FORMING STACKED PACKAGE Public/Granted day:2012-01-26
Information query
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