Invention Grant
US08486830B2 Via forming method and method of manufacturing multi-chip package using the same
有权
通过使用其制造多芯片封装的形成方法和方法
- Patent Title: Via forming method and method of manufacturing multi-chip package using the same
- Patent Title (中): 通过使用其制造多芯片封装的形成方法和方法
-
Application No.: US12835289Application Date: 2010-07-13
-
Publication No.: US08486830B2Publication Date: 2013-07-16
- Inventor: Dong Pyo Kim , Kyu Ha Baek , Kun Sik Park , Lee Mi Do
- Applicant: Dong Pyo Kim , Kyu Ha Baek , Kun Sik Park , Lee Mi Do
- Applicant Address: KR Daejeon
- Assignee: Electronics and Telecommunications Research Institute
- Current Assignee: Electronics and Telecommunications Research Institute
- Current Assignee Address: KR Daejeon
- Agency: Rabin & Berdo, P.C.
- Main IPC: H01L21/44
- IPC: H01L21/44
Abstract:
A via forming method that includes forming via-holes in a substrate is provided. The method includes putting the substrate, having the via-holes, in a first solution to fill the via-holes with the first solution. Metal particles are sunk into the via-holes by supplying a second solution containing the metal particles to the first solution. A first curing process of heat-treating the substrate is performed so as to form vias in the via-holes. A multi-chip package that includes the substrate having the vias is also provided.
Public/Granted literature
- US20110097853A1 VIA FORMING METHOD AND METHOD OF MANUFACTURING MULTI-CHIP PACKAGE USING THE SAME Public/Granted day:2011-04-28
Information query
IPC分类:
