Invention Grant
- Patent Title: Multiple data rate memory interface architecture
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Application No.: US13176284Application Date: 2011-07-05
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Publication No.: US08487651B2Publication Date: 2013-07-16
- Inventor: Andy L. Lee , Brian D. Johnson
- Applicant: Andy L. Lee , Brian D. Johnson
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agency: Ropes & Gray LLP
- Main IPC: H03K19/173
- IPC: H03K19/173
Abstract:
The present invention provides a DQS bus for implementing high speed multiple-data-rate interface architectures in programmable logic devices. The DQS bus has a balanced tree structure between at least one data strobe circuit and a plurality of I/O register blocks.
Public/Granted literature
- US20110260751A1 MULTIPLE DATA RATE MEMORY INTERFACE ARCHITECTURE Public/Granted day:2011-10-27
Information query
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