Invention Grant
US08487795B1 Time-interleaved track-and-hold circuit using distributed global sine-wave clock
失效
使用分布式全局正弦波时钟的时间交错跟踪和保持电路
- Patent Title: Time-interleaved track-and-hold circuit using distributed global sine-wave clock
- Patent Title (中): 使用分布式全局正弦波时钟的时间交错跟踪和保持电路
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Application No.: US13450204Application Date: 2012-04-18
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Publication No.: US08487795B1Publication Date: 2013-07-16
- Inventor: Tao Jiang , Patrick Yin Chiang , Freeman Y. Zhong
- Applicant: Tao Jiang , Patrick Yin Chiang , Freeman Y. Zhong
- Applicant Address: US CA San Jose US OR Corvallis
- Assignee: LSI Corporation,Oregon State University
- Current Assignee: LSI Corporation,Oregon State University
- Current Assignee Address: US CA San Jose US OR Corvallis
- Agency: Otterstedt, Ellenbogen & Kammer, LLP
- Main IPC: H03M1/00
- IPC: H03M1/00

Abstract:
A time-interleaved track-and-hold circuit includes a clock generator adapted to receive a global sine-wave clock signal and to generate therefrom multiple square-wave output clock signals of different phases. The track-and-hold circuit includes a switching array operative in at least a track mode or a hold mode. The switching array includes multiple switch circuits, each switch circuit adapted to receive an analog input signal, a corresponding one of the output clock signals, and the global sine-wave clock signal. Each switch circuit is operative to utilize the corresponding one of the output clock signals during the track mode for tracking the analog input signal, and is operative during the hold mode to store the input signal sampled during the track mode as an output of the switch circuit and to utilize the global sine-wave clock signal during the hold mode for synchronizing sampling instants of the respective outputs of the switch circuits.
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