A successive approximation AD conversion circuit has improved conversion accuracy without prolonging the time necessary for conversion. The successive approximation AD conversion circuit includes a plurality of amplifier stages cascaded together through coupling capacitances, and a comparator circuit which determines whether an input analog voltage is greater or less than comparison voltages. The comparator circuit includes a first comparator unit and a second comparator unit having a common initial amplifier stage among a plurality of amplifier stages, and, respectively, a first amplifier stage and second amplifier stage connected after the common stage through respective coupling capacitances; and first and second comparison point shift circuits connected respectively to input terminals of the first and second amplifier stages. The first and second comparison point shift circuits are configured to shift the comparison voltages by a specified amount in opposite directions, when amplifying the potential difference between the input analog voltage and the comparison voltages.