Methods and apparatus for optimizing the phase lock loop circuitry of sub-pixel clock generators for situations where frequent switching between different system printing speeds, and hence clock frequencies are required. A timing control logic circuitry is associated with the sub-pixel clock generator for a graduated change in charge pump current. The timing control logic circuitry comprises a plurality of current generators serially connected with the charge pump current via associated switches for the selective adjustment of charge pump current in a graduated manner.