Invention Grant
US08489907B2 Method of selective power cycling of components in a memory device independently by reducing power to a memory array or memory controller
有权
通过减少存储器阵列或存储器控制器的功率来独立地选择性地对存储器件中的部件进行功率循环的方法
- Patent Title: Method of selective power cycling of components in a memory device independently by reducing power to a memory array or memory controller
- Patent Title (中): 通过减少存储器阵列或存储器控制器的功率来独立地选择性地对存储器件中的部件进行功率循环的方法
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Application No.: US12561158Application Date: 2009-09-16
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Publication No.: US08489907B2Publication Date: 2013-07-16
- Inventor: Nir Jacob Wakrat , Anthony Fai , Matthew Byom
- Applicant: Nir Jacob Wakrat , Anthony Fai , Matthew Byom
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Myertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Main IPC: G06F1/00
- IPC: G06F1/00
Abstract:
In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.
Public/Granted literature
- US20110066869A1 Memory Array Power Cycling Public/Granted day:2011-03-17
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