Invention Grant
US08489919B2 Circuits and methods for processors with multiple redundancy techniques for mitigating radiation errors
有权
具有多种冗余技术的处理器的电路和方法，用于减轻辐射误差
- Patent Title: Circuits and methods for processors with multiple redundancy techniques for mitigating radiation errors
- Patent Title (中): 具有多种冗余技术的处理器的电路和方法，用于减轻辐射误差
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Application No.: US12626495Application Date: 2009-11-25
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Publication No.: US08489919B2Publication Date: 2013-07-16
- Inventor: Lawrence T. Clark , Dan W. Patterson
- Applicant: Lawrence T. Clark , Dan W. Patterson
- Applicant Address: US AZ Scottsdale
- Assignee: Arizona Board of Regents
- Current Assignee: Arizona Board of Regents
- Current Assignee Address: US AZ Scottsdale
- Agency: Withrow & Terranova, P.L.L.C.
- Main IPC: G06F11/00
- IPC: G06F11/00
Abstract:
Embodiments of circuits for processors with multiple redundancy techniques for mitigating radiation errors are described herein. Other embodiments and related methods and examples are also described herein.
Public/Granted literature
- US20100268987A1 Circuits And Methods For Processors With Multiple Redundancy Techniques For Mitigating Radiation Errors Public/Granted day:2010-10-21
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