Invention Grant
- Patent Title: Manufacturing method for semiconductor integrated device
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Application No.: US13742788Application Date: 2013-01-16
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Publication No.: US08492173B2Publication Date: 2013-07-23
- Inventor: Hiroshi Maki , Tsuyoshi Yokomori , Tatsuyuki Okubo
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Kawasaki-shi
- Assignee: Renesas Electonics Corporation
- Current Assignee: Renesas Electonics Corporation
- Current Assignee Address: JP Kawasaki-shi
- Agency: Miles & Stockbridge P.C.
- Priority: JP2007-160922 20070619; JP2007-164820 20070622; JP2008-099965 20080408
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.
Public/Granted literature
- US20130130408A1 MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED DEVICE Public/Granted day:2013-05-23
Information query
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