Semiconductor device manufacturing method

Invention Grant

US08492219B2 Semiconductor device manufacturing method 有权

Title translation: 半导体器件制造方法

Please log in to see more content

Patent Title: Semiconductor device manufacturing method
Patent Title (中): 半导体器件制造方法
Application No.: US13487295

Application Date: 2012-06-04
Publication No.: US08492219B2

Publication Date: 2013-07-23
Inventor: Masumi Saitoh , Toshinori Numata , Yukio Nakabayashi
Applicant: Masumi Saitoh , Toshinori Numata , Yukio Nakabayashi
Applicant Address: JP Tokyo
Assignee: Kabushiki Kaisha Toshiba
Current Assignee: Kabushiki Kaisha Toshiba
Current Assignee Address: JP Tokyo
Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
Main IPC: H01L21/8234
IPC: H01L21/8234 ; H01L21/337 ; H01L21/8232 ; H01L21/336 ; H01L21/00

Abstract:

In a semiconductor device manufacturing method, a first semiconductor region which includes a narrow portion and a wide portion is formed in an upper portion of a semiconductor substrate, a gate insulating film is formed on at least side surfaces of the narrow portion, a gate electrode is formed on the gate insulating film, a mask pattern that covers the wide portion is formed, ion implantation of an impurity is performed with the mask pattern as a mask to form an extension impurity region in the narrow portion, the mask pattern is removed, a heat treatment is performed to activate the impurity, a gate sidewall is formed on a side surface of the gate electrode, epitaxial growth of a semiconductor film is performed on the narrow portion and the wide portion after the formation of the gate sidewall, and source-drain regions is formed on both sides of the gate electrode.

Abstract(Chinese):

在半导体器件制造方法中，在半导体衬底的上部形成包括窄部分和宽部分的第一半导体区域，在所述窄部分的至少侧表面上形成栅极绝缘膜，栅电极形成在栅极绝缘膜上，形成覆盖该宽部的掩模图形，利用掩模图案作为掩模进行杂质的离子注入，以在狭窄部分形成延伸杂质区，除去掩模图案，执行热处理以激活杂质，在栅电极的侧表面上形成栅极侧壁，在形成栅极侧壁的狭窄部分和宽部分之后进行半导体膜的外延生长，源在栅电极的两侧形成有引线区域。

Public/Granted literature

US20120282743A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD Public/Granted day:2012-11-08

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺