Invention Grant
- Patent Title: Fully depleted SOI device with buried doped layer
- Patent Title (中): 具有掩埋掺杂层的完全耗尽的SOI器件
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Application No.: US13305206Application Date: 2011-11-28
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Publication No.: US08492844B2Publication Date: 2013-07-23
- Inventor: Gerhard Enders , Wolfgang Hoenlein , Franz Hofmann , Carlos Mazure
- Applicant: Gerhard Enders , Wolfgang Hoenlein , Franz Hofmann , Carlos Mazure
- Applicant Address: FR Bernin
- Assignee: Soitec
- Current Assignee: Soitec
- Current Assignee Address: FR Bernin
- Agency: Winston & Strawn LLP
- Priority: EP11290010 20110113
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L29/36 ; H01L21/8238

Abstract:
The present invention relates to a method for the manufacture of a semiconductor device by providing a first substrate; providing a doped layer in a surface region of the first substrate; providing a buried oxide layer on the doped layer; providing a semiconductor layer on the buried oxide layer to obtain a semiconductor-on-insulator (SeOI) wafer; removing the buried oxide layer and the semiconductor layer from a first region of the SeOI wafer while maintaining the buried oxide layer and the semiconductor layer in a second region of the SeOI water; providing an upper transistor in the second region by forming a back gate in or by the doped layer; and providing a lower transistor in the first region by forming source and drain regions in or by the doped layer.
Public/Granted literature
- US20120181609A1 FULLY DEPLETED SOI DEVICE WITH BURIED DOPED LAYER Public/Granted day:2012-07-19
Information query
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