- Patent Title: On-chip inductors with through-silicon-via fence for Q improvement
-
Application No.: US11868392Application Date: 2007-10-05
-
Publication No.: US08492872B2Publication Date: 2013-07-23
- Inventor: Li-Chun Yang , Ming-Ta Yang , Chao-Shun Hsu
- Applicant: Li-Chun Yang , Ming-Ta Yang , Chao-Shun Hsu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: K&L Gates LLP
- Main IPC: H01L27/08
- IPC: H01L27/08

Abstract:
A semiconductor structure for providing isolations for on-chip inductors comprises a semiconductor substrate, one or more on-chip inductors formed above the first semiconductor substrate, a plurality of through-silicon-vias formed through the first semiconductor substrate in a vicinity of the one or more on-chip inductors, and one or more conductors coupling at least one of the plurality of through-silicon-vias to a ground, wherein the plurality of through-silicon-vias provide isolations for the one or more on-chip inductors.
Public/Granted literature
- US20090090995A1 On-chip inductors with through-silicon-via fence for Q improvement Public/Granted day:2009-04-09
Information query
IPC分类: