Invention Grant
US08493107B2 Clock generator for generating output clock having non-harmonic relationship with input clock and related clock generating method thereof
有权
时钟发生器，用于产生与输入时钟非谐波关系的输出时钟及其相关的时钟产生方法
- Patent Title: Clock generator for generating output clock having non-harmonic relationship with input clock and related clock generating method thereof
- Patent Title (中): 时钟发生器，用于产生与输入时钟非谐波关系的输出时钟及其相关的时钟产生方法
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Application No.: US13170197Application Date: 2011-06-28
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Publication No.: US08493107B2Publication Date: 2013-07-23
- Inventor: Robert Bogdan Staszewski , Chi-Hsueh Wang
- Applicant: Robert Bogdan Staszewski , Chi-Hsueh Wang
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: Mediatek Inc.
- Current Assignee: Mediatek Inc.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H03L7/00
- IPC: H03L7/00
Abstract:
One clock generator includes an oscillator block, a delay circuit, and an output block. The oscillator block provides a first clock of multiple phases. The delay circuit delays at least one of said multiple phases of said first clock to generate a second clock of multiple phases. The output block generates a third clock by selecting signals from said multiple phases of said second clock, wherein said third clock has non-harmonic relationship with said first clock. Another exemplary clock generator includes an oscillator block and an output block. The oscillator block includes an oscillator arranged to provide a first clock, and a delay locked loop arranged to generate a second clock according to said first clock. The output block generates a third clock by selecting signals from said multiple phases, wherein said third clock has non-harmonic relationship with said first clock.
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