A system and method for synchronizing asynchronous input signals with reliability. Each of a first and a second storage element in a synchronizer receives a first clock signal in a first clock domain. The second storage element may also receive a first reset signal generated by a second clock signal in the first clock domain different from the first clock signal. The first storage element receives a combination of an asynchronous data input signal and the first reset signal. The data input signal may be generated from circuitry utilizing a second clock domain different from the first clock domain. The second storage element additionally receives an output of a second combination of a stored output value of the first storage element and a second reset signal generated from the first clock signal. The second storage element stores a stable output value based at least on the asynchronous data input signal.