Invention Grant
US08493118B2 Low power scannable latch 有权
低功耗可拆卸闩锁

Low power scannable latch
Abstract:
A scannable latch circuit is disclosed. In one embodiment, the scannable latch circuit includes a master latch, a slave latch, and a gating circuit coupled between the master latch and the slave latch. The slave latch may be implemented to support scan-shifting for test operations. Scan data received by the master latch may be provided to the slave latch through the gating circuit. The gating circuit may enable data to be transferred from the master latch to the slave latch when a scan enable signal is asserted. When the scan enable signal is deasserted, the gating circuit may cause the slave latch to output a constant (i.e. unchanging) state, regardless of the state of data stored in the master latch. This may result in power savings by inhibiting the slave latch from making state changes when scan-shifting operations are not in progress.
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