Invention Grant
US08493763B1 Self-timed match line cascading in a partitioned content addressable memory array
有权
自定义匹配线级联在分区内容可寻址存储器阵列中
- Patent Title: Self-timed match line cascading in a partitioned content addressable memory array
- Patent Title (中): 自定义匹配线级联在分区内容可寻址存储器阵列中
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Application No.: US13283422Application Date: 2011-10-27
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Publication No.: US08493763B1Publication Date: 2013-07-23
- Inventor: Dimitri Argyres
- Applicant: Dimitri Argyres
- Applicant Address: US CA Irvine
- Assignee: NetLogic Microsystems, Inc.
- Current Assignee: NetLogic Microsystems, Inc.
- Current Assignee Address: US CA Irvine
- Agency: Sterne, Kessler, Goldstein & Fox PLLC
- Main IPC: G11C15/00
- IPC: G11C15/00

Abstract:
A CAM array includes a plurality of regular rows and a reference row. Each regular row is partitioned into a plurality of row segments, with each row segment including a number of CAM cells coupled to a corresponding match line segment. The reference row generates self-timed control signals for corresponding segments of the regular rows. Control circuits selectively enable a respective row segment in response to a logical combination of match results in a previous row segment and an associated one of the self-timed control signals.
Information query