Invention Grant
US08493774B2 Performing logic functions on more than one memory cell within an array of memory cells
失效
在存储单元阵列内的多个存储单元上执行逻辑功能
- Patent Title: Performing logic functions on more than one memory cell within an array of memory cells
- Patent Title (中): 在存储单元阵列内的多个存储单元上执行逻辑功能
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Application No.: US13162753Application Date: 2011-06-17
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Publication No.: US08493774B2Publication Date: 2013-07-23
- Inventor: Jente B. Kuang , Rahul M. Rao
- Applicant: Jente B. Kuang , Rahul M. Rao
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Francis Lammes; Stephen J. Walder, Jr.; Eustus D. Nelson
- Main IPC: G11C11/00
- IPC: G11C11/00

Abstract:
A circuit structure is provided for performing a logic function within a memory. A plurality of read word line transistors are provided that receive a read word line signal and, upon receiving the read word line signal, the plurality of read word line transistors provide a path from a plurality of bit-line transistors associated with a plurality of physically adjacent memory cells to a read bit-line. In response to an associated memory cell within the memory storing a first value, each of the plurality of read bit-line transistors turns on and provides a path to ground thereby causing a first output value to be output on the read bit-line. In response to all of the plurality of memory cells storing a second value, the plurality of read bit-line transistors turn off thereby preventing a path to ground and a second output value is output on the read bit-line.
Public/Granted literature
- US20120320689A1 Performing Logic Functions on More Than One Memory Cell Within an Array of Memory Cells Public/Granted day:2012-12-20
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