Invention Grant
- Patent Title: Memory cell array latchup prevention
- Patent Title (中): 存储单元阵列闭锁预防
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Application No.: US13280937Application Date: 2011-10-25
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Publication No.: US08493804B2Publication Date: 2013-07-23
- Inventor: Ravindra M. Kapre , Shahin Sharifzadeh
- Applicant: Ravindra M. Kapre , Shahin Sharifzadeh
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G11C7/02
- IPC: G11C7/02
Abstract:
An embodiment includes configuring a current-limiting device to place along a power-supply bus to limit current through a first complimentary-metal-oxide semiconductor (CMOS) circuit coupled to the power-supply bus so that current does not exceed a trigger current level of a pnpn diode in a second CMOS circuit coupled to the power bus.
Public/Granted literature
- US20130135954A1 MEMORY CELL ARRAY LATCHUP PREVENTION Public/Granted day:2013-05-30
Information query
